Evaluasi Kinerja Metode Clock Recovery PLL Loop untuk Modulasi dan Demodulasi BPSK pada Dua Board DSK TMS320C6713
Submission Date: 2012-07-10 12:30:04
Accepted Date: 2012-09-11 00:00:00
Abstract
Radio merupakan perangkat telekomunikasi yang mengirim gelombang elektromagnetik dimana gelombang ini merambat melalui udara. Perangkat radio terdiri dari komponen elektronika analog yang digunakan untuk mengolah sinyal secara sederhana serta memiliki kemampuan yang terbatas. Komponen elektronika analog belum bisa memenuhi kebutuhan teknologi telekomunikasi saat ini, seperti laju bit tinggi dan perangkat yang kecil. Memasuki era digital mengakibatkan perkembangan komponen elektronika hingga saat ini muncul perangkat elektronika terprogram. Dalam tugas akhir ini, dilakukan pengujian kinerja dari salah satu metode clock recovery, yaitu phase-locked-loop yang akan dimasukkan ke dalam sistem demodulasi BPSK yang diimplementasikan pada sepasang board DSK TMS320C6000. Ada dua buah implementasi yang diuji dalam tugas akhir ini, yaitu implementasi modulasi dan demodulasi BPSK tanpa menggunakan PLL dan dengan menggunakannya. Dari hasil implementasi tersebut, kemudian diuji, dianalisis dan ditentukan berapa besar penurunan nilai BER-nya, sehingga bisa diketahui apakah penggunaan metode PLL dibutuhkan pada sistem modulasi dan demodulasi BPSK yang diimplementasikan pada DSK TMS320C6000.
Keywords
BPSK; DSK TMS320C6000; BER; SNR; phase-locked-loop
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